The invention relates to digital circuits and methods for testing a digital circuit.
It is often required to repeatedly verify correct operation of digital circuits, for example, microprocessors or microcontrollers. Especially in the field of automobiles it is vital to ensure correct operation of microprocessors or microcontrollers in control devices.
Known methods for testing functionality of a microprocessor in a control device, or more precisely of a core or central processing unit (CPU) of the processor, are for example, based on redundant systems. For this purpose two processors are provided with similar computing power. On both processors a respective control algorithm is executed. The results and sometimes also intermediate results are compared, for example, before activating respective output signals. If the results differ significantly an error in one of the two processors is assumed and the entire system is put into a “Fail Safe” state, for example, the system is shut down, to avoid incorrect controlling. However, as the control of the processor is performed during normal operation, errors which may lead to a shut down of the control system are first detected when the car is moved which may lead to dangerous situations for the driver.
Another approach for testing a CPU is to integrate a self test in the CPU, the so called built-in self test (BIST). The BIST requires dedicated circuitry to perform the self test of the processor. This, however, involves the necessity to ensure a complete error decoupling, which means that it has to be guaranteed that one single error does not change normal function of both the CPU and the self test logic. Thus, implementing a BIST functionality in a processor involves an increase in costs for development, design, and production.
An even further approach is the scan test for testing internal circuits in a processor. Similar to the BIST, the processors to be tested by a scan test have to be specially designed, that is, certain testability features have to be added to a microelectronic hardware product design to enable such tests. Accordingly, these design techniques are also called “Design for Test”. In scan-design, all storage elements (for example, registers, flip-flops or latches) include two operation modes. In the first mode, the storage elements operate according to their intended use in the digital circuit and, in the second mode, all storage elements are connected into a long shift-register (scan chain) which is used to gain access to internal nodes of the digital circuit. In general, some storage elements of the scan chain are connected to input pins to provide test data to the serial chain of storage elements and some storage elements of the scan chain are connected to output pins to allow for the processed test data to be read out.
However, when testing the digital circuit during normal operation of the circuit, two problems arise.
First, the state of the circuit after the test will differ from the state of the circuit before the test since test data has been input in the scan chain and processed in the circuit.
Second, during the scan test which requires a certain time, the circuit can not fulfil its intended function. For long scan chains the required time is particularly long as shifting the test data or test patterns in all the serial connected memory elements of the chain requires as many clocks as the number of memory elements contained in the chain is.
One approach to address the second problem is to divide a long sequential scan chain into several shorter partial scan chains. However one input/output pin pair has to be provided for every partial chain. In addition to the high number of required pins, the clock frequency for in-/output of data via external pins is generally significantly lower that the one for transmitting data within integrated elements.
Therefore, there exists a need for a design for a digital circuit and a method for testing a digital circuit, which, on the one hand, is cost-efficient (and therefore not limited to high priced special applications) and, on the other hand, provides a reliable test of a digital circuit during operation without interfering proper operation of the circuit and with minimal interruption of normal operation of the circuit.